#ifndef REG_SYSC_PER_H_
#define REG_SYSC_PER_H_

#include <stdint.h>
#include "reg_base_addr.h"

#ifdef __cplusplus
extern "C" {
#endif

#define SYSC_PER ((reg_sysc_per_t *)SYSC_PER_BASE_ADDR)
// #define SYSC_PER ((reg_sysc_per_t *)0x4008D000)

typedef struct
{
    volatile uint32_t PD_PER_CLKG0; //0x0
    volatile uint32_t PD_PER_CLKG1; //0x4
    volatile uint32_t PD_PER_CLKG2; //0x8
    volatile uint32_t PD_PER_CLKG3; //0xc
    volatile uint32_t PD_PER_SRST0; //0x10
    volatile uint32_t PD_PER_SRST1; //0x14
    volatile uint32_t PD_PER_SRST2; //0x18
    volatile uint32_t PD_PER_SRST3; //0x1c
    volatile uint32_t FUNC_SEL[32]; //0x20
    volatile uint32_t COMP_PIS; //0xa0
    volatile uint32_t PIS_SFT; //0xa4
    volatile uint32_t TIMER_UART; //0xa8
}reg_sysc_per_t;

enum SYSC_PER_REG_PD_PER_CLKG0_FIELD
{
    SYSC_PER_CLKG_SET_BSTIM1_MASK = (int)0x1,
    SYSC_PER_CLKG_SET_BSTIM1_POS = 0,
    SYSC_PER_CLKG_CLR_BSTIM1_MASK = (int)0x2,
    SYSC_PER_CLKG_CLR_BSTIM1_POS = 1,
    SYSC_PER_CLKG_SET_GPTIMA1_MASK = (int)0x4,
    SYSC_PER_CLKG_SET_GPTIMA1_POS = 2,
    SYSC_PER_CLKG_CLR_GPTIMA1_MASK = (int)0x8,
    SYSC_PER_CLKG_CLR_GPTIMA1_POS = 3,
    SYSC_PER_CLKG_SET_GPTIMA2_MASK = (int)0x10,
    SYSC_PER_CLKG_SET_GPTIMA2_POS = 4,
    SYSC_PER_CLKG_CLR_GPTIMA2_MASK = (int)0x20,
    SYSC_PER_CLKG_CLR_GPTIMA2_POS = 5,
    SYSC_PER_CLKG_SET_GPTIMB1_MASK = (int)0x40,
    SYSC_PER_CLKG_SET_GPTIMB1_POS = 6,
    SYSC_PER_CLKG_CLR_GPTIMB1_MASK = (int)0x80,
    SYSC_PER_CLKG_CLR_GPTIMB1_POS = 7,
    SYSC_PER_CLKG_SET_GPTIMC1_MASK = (int)0x100,
    SYSC_PER_CLKG_SET_GPTIMC1_POS = 8,
    SYSC_PER_CLKG_CLR_GPTIMC1_MASK = (int)0x200,
    SYSC_PER_CLKG_CLR_GPTIMC1_POS = 9,
    SYSC_PER_CLKG_SET_ADTIM1_MASK = (int)0x400,
    SYSC_PER_CLKG_SET_ADTIM1_POS = 10,
    SYSC_PER_CLKG_CLR_ADTIM1_MASK = (int)0x800,
    SYSC_PER_CLKG_CLR_ADTIM1_POS = 11,
    SYSC_PER_CLKG_SET_ADTIM2_MASK = (int)0x1000,
    SYSC_PER_CLKG_SET_ADTIM2_POS = 12,
    SYSC_PER_CLKG_CLR_ADTIM2_MASK = (int)0x2000,
    SYSC_PER_CLKG_CLR_ADTIM2_POS = 13,
    SYSC_PER_CLKG_SET_ADTIM3_MASK = (int)0x4000,
    SYSC_PER_CLKG_SET_ADTIM3_POS = 14,
    SYSC_PER_CLKG_CLR_ADTIM3_MASK = (int)0x8000,
    SYSC_PER_CLKG_CLR_ADTIM3_POS = 15,
    SYSC_PER_CLKG_SET_ADTIM4_MASK = (int)0x10000,
    SYSC_PER_CLKG_SET_ADTIM4_POS = 16,
    SYSC_PER_CLKG_CLR_ADTIM4_MASK = (int)0x20000,
    SYSC_PER_CLKG_CLR_ADTIM4_POS = 17,
    SYSC_PER_CLKG_SET_PWM_MASK = (int)0x40000,
    SYSC_PER_CLKG_SET_PWM_POS = 18,
    SYSC_PER_CLKG_CLR_PWM_MASK = (int)0x80000,
    SYSC_PER_CLKG_CLR_PWM_POS = 19,
    SYSC_PER_CLKG_SET_CAP_MASK = (int)0x100000,
    SYSC_PER_CLKG_SET_CAP_POS = 20,
    SYSC_PER_CLKG_CLR_CAP_MASK = (int)0x200000,
    SYSC_PER_CLKG_CLR_CAP_POS = 21,
    SYSC_PER_CLKG_SET_I2C1_MASK = (int)0x1000000,
    SYSC_PER_CLKG_SET_I2C1_POS = 24,
    SYSC_PER_CLKG_CLR_I2C1_MASK = (int)0x2000000,
    SYSC_PER_CLKG_CLR_I2C1_POS = 25,
    SYSC_PER_CLKG_SET_I2C2_MASK = (int)0x4000000,
    SYSC_PER_CLKG_SET_I2C2_POS = 26,
    SYSC_PER_CLKG_CLR_I2C2_MASK = (int)0x8000000,
    SYSC_PER_CLKG_CLR_I2C2_POS = 27,
    SYSC_PER_CLKG_SET_I2C3_MASK = (int)0x10000000,
    SYSC_PER_CLKG_SET_I2C3_POS = 28,
    SYSC_PER_CLKG_CLR_I2C3_MASK = (int)0x20000000,
    SYSC_PER_CLKG_CLR_I2C3_POS = 29,
    SYSC_PER_CLKG_SET_I2C4_MASK = (int)0x40000000,
    SYSC_PER_CLKG_SET_I2C4_POS = 30,
    SYSC_PER_CLKG_CLR_I2C4_MASK = (int)0x80000000,
    SYSC_PER_CLKG_CLR_I2C4_POS = 31,
};

enum SYSC_PER_REG_PD_PER_CLKG1_FIELD
{
    SYSC_PER_CLKG_SET_I2C5_MASK = (int)0x1,
    SYSC_PER_CLKG_SET_I2C5_POS = 0,
    SYSC_PER_CLKG_CLR_I2C5_MASK = (int)0x2,
    SYSC_PER_CLKG_CLR_I2C5_POS = 1,
    SYSC_PER_CLKG_SET_I2C6_MASK = (int)0x4,
    SYSC_PER_CLKG_SET_I2C6_POS = 2,
    SYSC_PER_CLKG_CLR_I2C6_MASK = (int)0x8,
    SYSC_PER_CLKG_CLR_I2C6_POS = 3,
    SYSC_PER_CLKG_SET_UART1_MASK = (int)0x100,
    SYSC_PER_CLKG_SET_UART1_POS = 8,
    SYSC_PER_CLKG_CLR_UART1_MASK = (int)0x200,
    SYSC_PER_CLKG_CLR_UART1_POS = 9,
    SYSC_PER_CLKG_SET_UART2_MASK = (int)0x400,
    SYSC_PER_CLKG_SET_UART2_POS = 10,
    SYSC_PER_CLKG_CLR_UART2_MASK = (int)0x800,
    SYSC_PER_CLKG_CLR_UART2_POS = 11,
    SYSC_PER_CLKG_SET_UART3_MASK = (int)0x1000,
    SYSC_PER_CLKG_SET_UART3_POS = 12,
    SYSC_PER_CLKG_CLR_UART3_MASK = (int)0x2000,
    SYSC_PER_CLKG_CLR_UART3_POS = 13,
    SYSC_PER_CLKG_SET_DWUART1_MASK = (int)0x4000,
    SYSC_PER_CLKG_SET_DWUART1_POS = 14,
    SYSC_PER_CLKG_CLR_DWUART1_MASK = (int)0x8000,
    SYSC_PER_CLKG_CLR_DWUART1_POS = 15,
    SYSC_PER_CLKG_SET_DWUART2_MASK = (int)0x10000,
    SYSC_PER_CLKG_SET_DWUART2_POS = 16,
    SYSC_PER_CLKG_CLR_DWUART2_MASK = (int)0x20000,
    SYSC_PER_CLKG_CLR_DWUART2_POS = 17,
    SYSC_PER_CLKG_SET_SPI1_MASK = (int)0x1000000,
    SYSC_PER_CLKG_SET_SPI1_POS = 24,
    SYSC_PER_CLKG_CLR_SPI1_MASK = (int)0x2000000,
    SYSC_PER_CLKG_CLR_SPI1_POS = 25,
    SYSC_PER_CLKG_SET_SPI2_MASK = (int)0x4000000,
    SYSC_PER_CLKG_SET_SPI2_POS = 26,
    SYSC_PER_CLKG_CLR_SPI2_MASK = (int)0x8000000,
    SYSC_PER_CLKG_CLR_SPI2_POS = 27,
    SYSC_PER_CLKG_SET_SPI3_MASK = (int)0x10000000,
    SYSC_PER_CLKG_SET_SPI3_POS = 28,
    SYSC_PER_CLKG_CLR_SPI3_MASK = (int)0x20000000,
    SYSC_PER_CLKG_CLR_SPI3_POS = 29,
    SYSC_PER_CLKG_SET_SPIS_MASK = (int)0x40000000,
    SYSC_PER_CLKG_SET_SPIS_POS = 30,
    SYSC_PER_CLKG_CLR_SPIS_MASK = (int)0x80000000,
    SYSC_PER_CLKG_CLR_SPIS_POS = 31,
};

enum SYSC_PER_REG_PD_PER_CLKG2_FIELD
{
    SYSC_PER_CLKG_SET_ADC1_MASK = (int)0x100,
    SYSC_PER_CLKG_SET_ADC1_POS = 8,
    SYSC_PER_CLKG_CLR_ADC1_MASK = (int)0x200,
    SYSC_PER_CLKG_CLR_ADC1_POS = 9,
    SYSC_PER_CLKG_SET_ADC2_MASK = (int)0x400,
    SYSC_PER_CLKG_SET_ADC2_POS = 10,
    SYSC_PER_CLKG_CLR_ADC2_MASK = (int)0x800,
    SYSC_PER_CLKG_CLR_ADC2_POS = 11,
    SYSC_PER_CLKG_SET_PDM_MASK = (int)0x10000,
    SYSC_PER_CLKG_SET_PDM_POS = 16,
    SYSC_PER_CLKG_CLR_PDM_MASK = (int)0x20000,
    SYSC_PER_CLKG_CLR_PDM_POS = 17,
    SYSC_PER_CLKG_SET_EXTI0_MASK = (int)0x1000000,
    SYSC_PER_CLKG_SET_EXTI0_POS = 24,
    SYSC_PER_CLKG_CLR_EXTI0_MASK = (int)0x2000000,
    SYSC_PER_CLKG_CLR_EXTI0_POS = 25,
    SYSC_PER_CLKG_SET_EXTI1_MASK = (int)0x4000000,
    SYSC_PER_CLKG_SET_EXTI1_POS = 26,
    SYSC_PER_CLKG_CLR_EXTI1_MASK = (int)0x8000000,
    SYSC_PER_CLKG_CLR_EXTI1_POS = 27,
};

enum SYSC_PER_REG_PD_PER_CLKG3_FIELD
{
    SYSC_PER_CLKG_SET_WWDT_MASK = (int)0x1,
    SYSC_PER_CLKG_SET_WWDT_POS = 0,
    SYSC_PER_CLKG_CLR_WWDT_MASK = (int)0x2,
    SYSC_PER_CLKG_CLR_WWDT_POS = 1,
    SYSC_PER_CLKG_SET_PIS_MASK = (int)0x4,
    SYSC_PER_CLKG_SET_PIS_POS = 2,
    SYSC_PER_CLKG_CLR_PIS_MASK = (int)0x8,
    SYSC_PER_CLKG_CLR_PIS_POS = 3,
    SYSC_PER_CLKG_SET_TK_MASK = (int)0x10,
    SYSC_PER_CLKG_SET_TK_POS = 4,
    SYSC_PER_CLKG_CLR_TK_MASK = (int)0x20,
    SYSC_PER_CLKG_CLR_TK_POS = 5,
    SYSC_PER_CLKG_SET_TRNG_MASK = (int)0x40,
    SYSC_PER_CLKG_SET_TRNG_POS = 6,
    SYSC_PER_CLKG_CLR_TRNG_MASK = (int)0x80,
    SYSC_PER_CLKG_CLR_TRNG_POS = 7,
    SYSC_PER_CLKG_SET_DAC12_MASK = (int)0x400,
    SYSC_PER_CLKG_SET_DAC12_POS = 10,
    SYSC_PER_CLKG_CLR_DAC12_MASK = (int)0x800,
    SYSC_PER_CLKG_CLR_DAC12_POS = 11,
    SYSC_PER_CLKG_SET_KSCAN_MASK = (int)0x1000,
    SYSC_PER_CLKG_SET_KSCAN_POS = 12,
    SYSC_PER_CLKG_CLR_KSCAN_MASK = (int)0x2000,
    SYSC_PER_CLKG_CLR_KSCAN_POS = 13,
    SYSC_PER_CLKG_SET_OWM_MASK = (int)0x4000,
    SYSC_PER_CLKG_SET_OWM_POS = 14,
    SYSC_PER_CLKG_CLR_OWM_MASK = (int)0x8000,
    SYSC_PER_CLKG_CLR_OWM_POS = 15,
    SYSC_PER_CLKG_SET_PS2H1_MASK = (int)0x10000,
    SYSC_PER_CLKG_SET_PS2H1_POS = 16,
    SYSC_PER_CLKG_CLR_PS2H1_MASK = (int)0x20000,
    SYSC_PER_CLKG_CLR_PS2H1_POS = 17,
    SYSC_PER_CLKG_SET_PS2H2_MASK = (int)0x40000,
    SYSC_PER_CLKG_SET_PS2H2_POS = 18,
    SYSC_PER_CLKG_CLR_PS2H2_MASK = (int)0x80000,
    SYSC_PER_CLKG_CLR_PS2H2_POS = 19,
    SYSC_PER_CLKG_SET_PS2H3_MASK = (int)0x100000,
    SYSC_PER_CLKG_SET_PS2H3_POS = 20,
    SYSC_PER_CLKG_CLR_PS2H3_MASK = (int)0x200000,
    SYSC_PER_CLKG_CLR_PS2H3_POS = 21,
    SYSC_PER_CLKG_SET_PS2H4_MASK = (int)0x400000,
    SYSC_PER_CLKG_SET_PS2H4_POS = 22,
    SYSC_PER_CLKG_CLR_PS2H4_MASK = (int)0x800000,
    SYSC_PER_CLKG_CLR_PS2H4_POS = 23,
    SYSC_PER_CLKG_SET_CEC_MASK = (int)0x1000000,
    SYSC_PER_CLKG_SET_CEC_POS = 24,
    SYSC_PER_CLKG_CLR_CEC_MASK = (int)0x2000000,
    SYSC_PER_CLKG_CLR_CEC_POS = 25,
    SYSC_PER_CLKG_SET_PECI_MASK = (int)0x4000000,
    SYSC_PER_CLKG_SET_PECI_POS = 26,
    SYSC_PER_CLKG_CLR_PECI_MASK = (int)0x8000000,
    SYSC_PER_CLKG_CLR_PECI_POS = 27,
    SYSC_PER_CLKG_SET_FILTER_MASK = (int)0x10000000,
    SYSC_PER_CLKG_SET_FILTER_POS = 28,
    SYSC_PER_CLKG_CLR_FILTER_MASK = (int)0x20000000,
    SYSC_PER_CLKG_CLR_FILTER_POS = 29,
};

enum SYSC_PER_REG_PD_PER_SRST0_FIELD
{
    SYSC_PER_SRST_SET_BSTIM1_N_MASK = (int)0x1,
    SYSC_PER_SRST_SET_BSTIM1_N_POS = 0,
    SYSC_PER_SRST_CLR_BSTIM1_N_MASK = (int)0x2,
    SYSC_PER_SRST_CLR_BSTIM1_N_POS = 1,
    SYSC_PER_SRST_SET_GPTIMA1_N_MASK = (int)0x4,
    SYSC_PER_SRST_SET_GPTIMA1_N_POS = 2,
    SYSC_PER_SRST_CLR_GPTIMA1_N_MASK = (int)0x8,
    SYSC_PER_SRST_CLR_GPTIMA1_N_POS = 3,
    SYSC_PER_SRST_SET_GPTIMA2_N_MASK = (int)0x10,
    SYSC_PER_SRST_SET_GPTIMA2_N_POS = 4,
    SYSC_PER_SRST_CLR_GPTIMA2_N_MASK = (int)0x20,
    SYSC_PER_SRST_CLR_GPTIMA2_N_POS = 5,
    SYSC_PER_SRST_SET_GPTIMB1_N_MASK = (int)0x40,
    SYSC_PER_SRST_SET_GPTIMB1_N_POS = 6,
    SYSC_PER_SRST_CLR_GPTIMB1_N_MASK = (int)0x80,
    SYSC_PER_SRST_CLR_GPTIMB1_N_POS = 7,
    SYSC_PER_SRST_SET_GPTIMC1_N_MASK = (int)0x100,
    SYSC_PER_SRST_SET_GPTIMC1_N_POS = 8,
    SYSC_PER_SRST_CLR_GPTIMC1_N_MASK = (int)0x200,
    SYSC_PER_SRST_CLR_GPTIMC1_N_POS = 9,
    SYSC_PER_SRST_SET_ADTIM1_N_MASK = (int)0x400,
    SYSC_PER_SRST_SET_ADTIM1_N_POS = 10,
    SYSC_PER_SRST_CLR_ADTIM1_N_MASK = (int)0x800,
    SYSC_PER_SRST_CLR_ADTIM1_N_POS = 11,
    SYSC_PER_SRST_SET_ADTIM2_N_MASK = (int)0x1000,
    SYSC_PER_SRST_SET_ADTIM2_N_POS = 12,
    SYSC_PER_SRST_CLR_ADTIM2_N_MASK = (int)0x2000,
    SYSC_PER_SRST_CLR_ADTIM2_N_POS = 13,
    SYSC_PER_SRST_SET_ADTIM3_N_MASK = (int)0x4000,
    SYSC_PER_SRST_SET_ADTIM3_N_POS = 14,
    SYSC_PER_SRST_CLR_ADTIM3_N_MASK = (int)0x8000,
    SYSC_PER_SRST_CLR_ADTIM3_N_POS = 15,
    SYSC_PER_SRST_SET_ADTIM4_N_MASK = (int)0x10000,
    SYSC_PER_SRST_SET_ADTIM4_N_POS = 16,
    SYSC_PER_SRST_CLR_ADTIM4_N_MASK = (int)0x20000,
    SYSC_PER_SRST_CLR_ADTIM4_N_POS = 17,
    SYSC_PER_SRST_SET_PWM_N_MASK = (int)0x40000,
    SYSC_PER_SRST_SET_PWM_N_POS = 18,
    SYSC_PER_SRST_CLR_PWM_N_MASK = (int)0x80000,
    SYSC_PER_SRST_CLR_PWM_N_POS = 19,
    SYSC_PER_SRST_SET_CAP_N_MASK = (int)0x100000,
    SYSC_PER_SRST_SET_CAP_N_POS = 20,
    SYSC_PER_SRST_CLR_CAP_N_MASK = (int)0x200000,
    SYSC_PER_SRST_CLR_CAP_N_POS = 21,
    SYSC_PER_SRST_SET_I2C1_N_MASK = (int)0x1000000,
    SYSC_PER_SRST_SET_I2C1_N_POS = 24,
    SYSC_PER_SRST_CLR_I2C1_N_MASK = (int)0x2000000,
    SYSC_PER_SRST_CLR_I2C1_N_POS = 25,
    SYSC_PER_SRST_SET_I2C2_N_MASK = (int)0x4000000,
    SYSC_PER_SRST_SET_I2C2_N_POS = 26,
    SYSC_PER_SRST_CLR_I2C2_N_MASK = (int)0x8000000,
    SYSC_PER_SRST_CLR_I2C2_N_POS = 27,
    SYSC_PER_SRST_SET_I2C3_N_MASK = (int)0x10000000,
    SYSC_PER_SRST_SET_I2C3_N_POS = 28,
    SYSC_PER_SRST_CLR_I2C3_N_MASK = (int)0x20000000,
    SYSC_PER_SRST_CLR_I2C3_N_POS = 29,
    SYSC_PER_SRST_SET_I2C4_N_MASK = (int)0x40000000,
    SYSC_PER_SRST_SET_I2C4_N_POS = 30,
    SYSC_PER_SRST_CLR_I2C4_N_MASK = (int)0x80000000,
    SYSC_PER_SRST_CLR_I2C4_N_POS = 31,
};

enum SYSC_PER_REG_PD_PER_SRST1_FIELD
{
    SYSC_PER_SRST_SET_I2C5_N_MASK = (int)0x1,
    SYSC_PER_SRST_SET_I2C5_N_POS = 0,
    SYSC_PER_SRST_CLR_I2C5_N_MASK = (int)0x2,
    SYSC_PER_SRST_CLR_I2C5_N_POS = 1,
    SYSC_PER_SRST_SET_I2C6_N_MASK = (int)0x4,
    SYSC_PER_SRST_SET_I2C6_N_POS = 2,
    SYSC_PER_SRST_CLR_I2C6_N_MASK = (int)0x8,
    SYSC_PER_SRST_CLR_I2C6_N_POS = 3,
    SYSC_PER_SRST_SET_UART1_N_MASK = (int)0x100,
    SYSC_PER_SRST_SET_UART1_N_POS = 8,
    SYSC_PER_SRST_CLR_UART1_N_MASK = (int)0x200,
    SYSC_PER_SRST_CLR_UART1_N_POS = 9,
    SYSC_PER_SRST_SET_UART2_N_MASK = (int)0x400,
    SYSC_PER_SRST_SET_UART2_N_POS = 10,
    SYSC_PER_SRST_CLR_UART2_N_MASK = (int)0x800,
    SYSC_PER_SRST_CLR_UART2_N_POS = 11,
    SYSC_PER_SRST_SET_UART3_N_MASK = (int)0x1000,
    SYSC_PER_SRST_SET_UART3_N_POS = 12,
    SYSC_PER_SRST_CLR_UART3_N_MASK = (int)0x2000,
    SYSC_PER_SRST_CLR_UART3_N_POS = 13,
    SYSC_PER_SRST_SET_DWUART1_N_MASK = (int)0x4000,
    SYSC_PER_SRST_SET_DWUART1_N_POS = 14,
    SYSC_PER_SRST_CLR_DWUART1_N_MASK = (int)0x8000,
    SYSC_PER_SRST_CLR_DWUART1_N_POS = 15,
    SYSC_PER_SRST_SET_DWUART2_N_MASK = (int)0x10000,
    SYSC_PER_SRST_SET_DWUART2_N_POS = 16,
    SYSC_PER_SRST_CLR_DWUART2_N_MASK = (int)0x20000,
    SYSC_PER_SRST_CLR_DWUART2_N_POS = 17,
    SYSC_PER_SRST_SET_SPI1_N_MASK = (int)0x1000000,
    SYSC_PER_SRST_SET_SPI1_N_POS = 24,
    SYSC_PER_SRST_CLR_SPI1_N_MASK = (int)0x2000000,
    SYSC_PER_SRST_CLR_SPI1_N_POS = 25,
    SYSC_PER_SRST_SET_SPI2_N_MASK = (int)0x4000000,
    SYSC_PER_SRST_SET_SPI2_N_POS = 26,
    SYSC_PER_SRST_CLR_SPI2_N_MASK = (int)0x8000000,
    SYSC_PER_SRST_CLR_SPI2_N_POS = 27,
    SYSC_PER_SRST_SET_SPI3_N_MASK = (int)0x10000000,
    SYSC_PER_SRST_SET_SPI3_N_POS = 28,
    SYSC_PER_SRST_CLR_SPI3_N_MASK = (int)0x20000000,
    SYSC_PER_SRST_CLR_SPI3_N_POS = 29,
    SYSC_PER_SRST_SET_SPIS_N_MASK = (int)0x40000000,
    SYSC_PER_SRST_SET_SPIS_N_POS = 30,
    SYSC_PER_SRST_CLR_SPIS_N_MASK = (int)0x80000000,
    SYSC_PER_SRST_CLR_SPIS_N_POS = 31,
};

enum SYSC_PER_REG_PD_PER_SRST2_FIELD
{
    SYSC_PER_SRST_SET_ADC1_N_MASK = (int)0x100,
    SYSC_PER_SRST_SET_ADC1_N_POS = 8,
    SYSC_PER_SRST_CLR_ADC1_N_MASK = (int)0x200,
    SYSC_PER_SRST_CLR_ADC1_N_POS = 9,
    SYSC_PER_SRST_SET_ADC2_N_MASK = (int)0x400,
    SYSC_PER_SRST_SET_ADC2_N_POS = 10,
    SYSC_PER_SRST_CLR_ADC2_N_MASK = (int)0x800,
    SYSC_PER_SRST_CLR_ADC2_N_POS = 11,
    SYSC_PER_SRST_SET_PDM_N_MASK = (int)0x10000,
    SYSC_PER_SRST_SET_PDM_N_POS = 16,
    SYSC_PER_SRST_CLR_PDM_N_MASK = (int)0x20000,
    SYSC_PER_SRST_CLR_PDM_N_POS = 17,
    SYSC_PER_SRST_SET_EXTI0_N_MASK = (int)0x1000000,
    SYSC_PER_SRST_SET_EXTI0_N_POS = 24,
    SYSC_PER_SRST_CLR_EXTI0_N_MASK = (int)0x2000000,
    SYSC_PER_SRST_CLR_EXTI0_N_POS = 25,
    SYSC_PER_SRST_SET_EXTI1_N_MASK = (int)0x4000000,
    SYSC_PER_SRST_SET_EXTI1_N_POS = 26,
    SYSC_PER_SRST_CLR_EXTI1_N_MASK = (int)0x8000000,
    SYSC_PER_SRST_CLR_EXTI1_N_POS = 27,
};

enum SYSC_PER_REG_PD_PER_SRST3_FIELD
{
    SYSC_PER_SRST_SET_WWDT_N_MASK = (int)0x1,
    SYSC_PER_SRST_SET_WWDT_N_POS = 0,
    SYSC_PER_SRST_CLR_WWDT_N_MASK = (int)0x2,
    SYSC_PER_SRST_CLR_WWDT_N_POS = 1,
    SYSC_PER_SRST_SET_PIS_N_MASK = (int)0x4,
    SYSC_PER_SRST_SET_PIS_N_POS = 2,
    SYSC_PER_SRST_CLR_PIS_N_MASK = (int)0x8,
    SYSC_PER_SRST_CLR_PIS_N_POS = 3,
    SYSC_PER_SRST_SET_TK_N_MASK = (int)0x10,
    SYSC_PER_SRST_SET_TK_N_POS = 4,
    SYSC_PER_SRST_CLR_TK_N_MASK = (int)0x20,
    SYSC_PER_SRST_CLR_TK_N_POS = 5,
    SYSC_PER_SRST_SET_TRNG_N_MASK = (int)0x40,
    SYSC_PER_SRST_SET_TRNG_N_POS = 6,
    SYSC_PER_SRST_CLR_TRNG_N_MASK = (int)0x80,
    SYSC_PER_SRST_CLR_TRNG_N_POS = 7,
    SYSC_PER_SRST_SET_DAC12_N_MASK = (int)0x400,
    SYSC_PER_SRST_SET_DAC12_N_POS = 10,
    SYSC_PER_SRST_CLR_DAC12_N_MASK = (int)0x800,
    SYSC_PER_SRST_CLR_DAC12_N_POS = 11,
    SYSC_PER_SRST_SET_KSCAN_N_MASK = (int)0x1000,
    SYSC_PER_SRST_SET_KSCAN_N_POS = 12,
    SYSC_PER_SRST_CLR_KSCAN_N_MASK = (int)0x2000,
    SYSC_PER_SRST_CLR_KSCAN_N_POS = 13,
    SYSC_PER_SRST_SET_OWM_MASK = (int)0x4000,
    SYSC_PER_SRST_SET_OWM_POS = 14,
    SYSC_PER_SRST_CLR_OWM_MASK = (int)0x8000,
    SYSC_PER_SRST_CLR_OWM_POS = 15,
    SYSC_PER_SRST_SET_PS2H1_MASK = (int)0x10000,
    SYSC_PER_SRST_SET_PS2H1_POS = 16,
    SYSC_PER_SRST_CLR_PS2H1_MASK = (int)0x20000,
    SYSC_PER_SRST_CLR_PS2H1_POS = 17,
    SYSC_PER_SRST_SET_PS2H2_MASK = (int)0x40000,
    SYSC_PER_SRST_SET_PS2H2_POS = 18,
    SYSC_PER_SRST_CLR_PS2H2_MASK = (int)0x80000,
    SYSC_PER_SRST_CLR_PS2H2_POS = 19,
    SYSC_PER_SRST_SET_PS2H3_MASK = (int)0x100000,
    SYSC_PER_SRST_SET_PS2H3_POS = 20,
    SYSC_PER_SRST_CLR_PS2H3_MASK = (int)0x200000,
    SYSC_PER_SRST_CLR_PS2H3_POS = 21,
    SYSC_PER_SRST_SET_PS2H4_MASK = (int)0x400000,
    SYSC_PER_SRST_SET_PS2H4_POS = 22,
    SYSC_PER_SRST_CLR_PS2H4_MASK = (int)0x800000,
    SYSC_PER_SRST_CLR_PS2H4_POS = 23,
    SYSC_PER_SRST_SET_CEC_MASK = (int)0x1000000,
    SYSC_PER_SRST_SET_CEC_POS = 24,
    SYSC_PER_SRST_CLR_CEC_MASK = (int)0x2000000,
    SYSC_PER_SRST_CLR_CEC_POS = 25,
    SYSC_PER_SRST_SET_PECI_MASK = (int)0x4000000,
    SYSC_PER_SRST_SET_PECI_POS = 26,
    SYSC_PER_SRST_CLR_PECI_MASK = (int)0x8000000,
    SYSC_PER_SRST_CLR_PECI_POS = 27,
    SYSC_PER_SRST_SET_FILTER_MASK = (int)0x10000000,
    SYSC_PER_SRST_SET_FILTER_POS = 28,
    SYSC_PER_SRST_CLR_FILTER_MASK = (int)0x20000000,
    SYSC_PER_SRST_CLR_FILTER_POS = 29,
};

enum SYSC_PER_REG_FUNC_SEL0_FIELD
{
    SYSC_PER_FUNC_IO000_SEL_MASK = (int)0x7f,
    SYSC_PER_FUNC_IO000_SEL_POS = 0,
    SYSC_PER_FUNC_IO001_SEL_MASK = (int)0x7f00,
    SYSC_PER_FUNC_IO001_SEL_POS = 8,
    SYSC_PER_FUNC_IO002_SEL_MASK = (int)0x7f0000,
    SYSC_PER_FUNC_IO002_SEL_POS = 16,
    SYSC_PER_FUNC_IO003_SEL_MASK = (int)0x7f000000,
    SYSC_PER_FUNC_IO003_SEL_POS = 24,
};

enum SYSC_PER_REG_FUNC_SEL1_FIELD
{
    SYSC_PER_FUNC_IO004_SEL_MASK = (int)0x7f,
    SYSC_PER_FUNC_IO004_SEL_POS = 0,
    SYSC_PER_FUNC_IO005_SEL_MASK = (int)0x7f00,
    SYSC_PER_FUNC_IO005_SEL_POS = 8,
    SYSC_PER_FUNC_IO006_SEL_MASK = (int)0x7f0000,
    SYSC_PER_FUNC_IO006_SEL_POS = 16,
    SYSC_PER_FUNC_IO007_SEL_MASK = (int)0x7f000000,
    SYSC_PER_FUNC_IO007_SEL_POS = 24,
};

enum SYSC_PER_REG_FUNC_SEL2_FIELD
{
    SYSC_PER_FUNC_IO008_SEL_MASK = (int)0x7f,
    SYSC_PER_FUNC_IO008_SEL_POS = 0,
    SYSC_PER_FUNC_IO009_SEL_MASK = (int)0x7f00,
    SYSC_PER_FUNC_IO009_SEL_POS = 8,
    SYSC_PER_FUNC_IO010_SEL_MASK = (int)0x7f0000,
    SYSC_PER_FUNC_IO010_SEL_POS = 16,
    SYSC_PER_FUNC_IO011_SEL_MASK = (int)0x7f000000,
    SYSC_PER_FUNC_IO011_SEL_POS = 24,
};

enum SYSC_PER_REG_FUNC_SEL3_FIELD
{
    SYSC_PER_FUNC_IO012_SEL_MASK = (int)0x7f,
    SYSC_PER_FUNC_IO012_SEL_POS = 0,
    SYSC_PER_FUNC_IO013_SEL_MASK = (int)0x7f00,
    SYSC_PER_FUNC_IO013_SEL_POS = 8,
    SYSC_PER_FUNC_IO014_SEL_MASK = (int)0x7f0000,
    SYSC_PER_FUNC_IO014_SEL_POS = 16,
    SYSC_PER_FUNC_IO015_SEL_MASK = (int)0x7f000000,
    SYSC_PER_FUNC_IO015_SEL_POS = 24,
};

enum SYSC_PER_REG_FUNC_SEL4_FIELD
{
    SYSC_PER_FUNC_IO16_SEL_MASK = (int)0x7f,
    SYSC_PER_FUNC_IO16_SEL_POS = 0,
    SYSC_PER_FUNC_IO17_SEL_MASK = (int)0x7f00,
    SYSC_PER_FUNC_IO17_SEL_POS = 8,
    SYSC_PER_FUNC_IO18_SEL_MASK = (int)0x7f0000,
    SYSC_PER_FUNC_IO18_SEL_POS = 16,
    SYSC_PER_FUNC_IO19_SEL_MASK = (int)0x7f000000,
    SYSC_PER_FUNC_IO19_SEL_POS = 24,
};

enum SYSC_PER_REG_FUNC_SEL5_FIELD
{
    SYSC_PER_FUNC_IO020_SEL_MASK = (int)0x7f,
    SYSC_PER_FUNC_IO020_SEL_POS = 0,
    SYSC_PER_FUNC_IO021_SEL_MASK = (int)0x7f00,
    SYSC_PER_FUNC_IO021_SEL_POS = 8,
    SYSC_PER_FUNC_IO022_SEL_MASK = (int)0x7f0000,
    SYSC_PER_FUNC_IO022_SEL_POS = 16,
    SYSC_PER_FUNC_IO023_SEL_MASK = (int)0x7f000000,
    SYSC_PER_FUNC_IO023_SEL_POS = 24,
};

enum SYSC_PER_REG_FUNC_SEL6_FIELD
{
    SYSC_PER_FUNC_IO024_SEL_MASK = (int)0x7f,
    SYSC_PER_FUNC_IO024_SEL_POS = 0,
    SYSC_PER_FUNC_IO025_SEL_MASK = (int)0x7f00,
    SYSC_PER_FUNC_IO025_SEL_POS = 8,
    SYSC_PER_FUNC_IO026_SEL_MASK = (int)0x7f0000,
    SYSC_PER_FUNC_IO026_SEL_POS = 16,
    SYSC_PER_FUNC_IO027_SEL_MASK = (int)0x7f000000,
    SYSC_PER_FUNC_IO027_SEL_POS = 24,
};

enum SYSC_PER_REG_FUNC_SEL7_FIELD
{
    SYSC_PER_FUNC_IO028_SEL_MASK = (int)0x7f,
    SYSC_PER_FUNC_IO028_SEL_POS = 0,
    SYSC_PER_FUNC_IO029_SEL_MASK = (int)0x7f00,
    SYSC_PER_FUNC_IO029_SEL_POS = 8,
    SYSC_PER_FUNC_IO030_SEL_MASK = (int)0x7f0000,
    SYSC_PER_FUNC_IO030_SEL_POS = 16,
    SYSC_PER_FUNC_IO031_SEL_MASK = (int)0x7f000000,
    SYSC_PER_FUNC_IO031_SEL_POS = 24,
};

enum SYSC_PER_REG_FUNC_SEL8_FIELD
{
    SYSC_PER_FUNC_IO032_SEL_MASK = (int)0x7f,
    SYSC_PER_FUNC_IO032_SEL_POS = 0,
    SYSC_PER_FUNC_IO033_SEL_MASK = (int)0x7f00,
    SYSC_PER_FUNC_IO033_SEL_POS = 8,
    SYSC_PER_FUNC_IO034_SEL_MASK = (int)0x7f0000,
    SYSC_PER_FUNC_IO034_SEL_POS = 16,
    SYSC_PER_FUNC_IO035_SEL_MASK = (int)0x7f000000,
    SYSC_PER_FUNC_IO035_SEL_POS = 24,
};

enum SYSC_PER_REG_FUNC_SEL9_FIELD
{
    SYSC_PER_FUNC_IO036_SEL_MASK = (int)0x7f,
    SYSC_PER_FUNC_IO036_SEL_POS = 0,
    SYSC_PER_FUNC_IO037_SEL_MASK = (int)0x7f00,
    SYSC_PER_FUNC_IO037_SEL_POS = 8,
    SYSC_PER_FUNC_IO038_SEL_MASK = (int)0x7f0000,
    SYSC_PER_FUNC_IO038_SEL_POS = 16,
    SYSC_PER_FUNC_IO039_SEL_MASK = (int)0x7f000000,
    SYSC_PER_FUNC_IO039_SEL_POS = 24,
};

enum SYSC_PER_REG_FUNC_SEL10_FIELD
{
    SYSC_PER_FUNC_IO040_SEL_MASK = (int)0x7f,
    SYSC_PER_FUNC_IO040_SEL_POS = 0,
    SYSC_PER_FUNC_IO041_SEL_MASK = (int)0x7f00,
    SYSC_PER_FUNC_IO041_SEL_POS = 8,
    SYSC_PER_FUNC_IO042_SEL_MASK = (int)0x7f0000,
    SYSC_PER_FUNC_IO042_SEL_POS = 16,
    SYSC_PER_FUNC_IO043_SEL_MASK = (int)0x7f000000,
    SYSC_PER_FUNC_IO043_SEL_POS = 24,
};

enum SYSC_PER_REG_FUNC_SEL11_FIELD
{
    SYSC_PER_FUNC_IO044_SEL_MASK = (int)0x7f,
    SYSC_PER_FUNC_IO044_SEL_POS = 0,
    SYSC_PER_FUNC_IO045_SEL_MASK = (int)0x7f00,
    SYSC_PER_FUNC_IO045_SEL_POS = 8,
    SYSC_PER_FUNC_IO046_SEL_MASK = (int)0x7f0000,
    SYSC_PER_FUNC_IO046_SEL_POS = 16,
    SYSC_PER_FUNC_IO047_SEL_MASK = (int)0x7f000000,
    SYSC_PER_FUNC_IO047_SEL_POS = 24,
};

enum SYSC_PER_REG_FUNC_SEL12_FIELD
{
    SYSC_PER_FUNC_IO048_SEL_MASK = (int)0x7f,
    SYSC_PER_FUNC_IO048_SEL_POS = 0,
    SYSC_PER_FUNC_IO049_SEL_MASK = (int)0x7f00,
    SYSC_PER_FUNC_IO049_SEL_POS = 8,
    SYSC_PER_FUNC_IO050_SEL_MASK = (int)0x7f0000,
    SYSC_PER_FUNC_IO050_SEL_POS = 16,
    SYSC_PER_FUNC_IO051_SEL_MASK = (int)0x7f000000,
    SYSC_PER_FUNC_IO051_SEL_POS = 24,
};

enum SYSC_PER_REG_FUNC_SEL13_FIELD
{
    SYSC_PER_FUNC_IO052_SEL_MASK = (int)0x7f,
    SYSC_PER_FUNC_IO052_SEL_POS = 0,
    SYSC_PER_FUNC_IO053_SEL_MASK = (int)0x7f00,
    SYSC_PER_FUNC_IO053_SEL_POS = 8,
    SYSC_PER_FUNC_IO054_SEL_MASK = (int)0x7f0000,
    SYSC_PER_FUNC_IO054_SEL_POS = 16,
    SYSC_PER_FUNC_IO055_SEL_MASK = (int)0x7f000000,
    SYSC_PER_FUNC_IO055_SEL_POS = 24,
};

enum SYSC_PER_REG_FUNC_SEL14_FIELD
{
    SYSC_PER_FUNC_IO056_SEL_MASK = (int)0x7f,
    SYSC_PER_FUNC_IO056_SEL_POS = 0,
    SYSC_PER_FUNC_IO057_SEL_MASK = (int)0x7f00,
    SYSC_PER_FUNC_IO057_SEL_POS = 8,
    SYSC_PER_FUNC_IO058_SEL_MASK = (int)0x7f0000,
    SYSC_PER_FUNC_IO058_SEL_POS = 16,
    SYSC_PER_FUNC_IO059_SEL_MASK = (int)0x7f000000,
    SYSC_PER_FUNC_IO059_SEL_POS = 24,
};

enum SYSC_PER_REG_FUNC_SEL15_FIELD
{
    SYSC_PER_FUNC_IO060_SEL_MASK = (int)0x7f,
    SYSC_PER_FUNC_IO060_SEL_POS = 0,
    SYSC_PER_FUNC_IO061_SEL_MASK = (int)0x7f00,
    SYSC_PER_FUNC_IO061_SEL_POS = 8,
    SYSC_PER_FUNC_IO062_SEL_MASK = (int)0x7f0000,
    SYSC_PER_FUNC_IO062_SEL_POS = 16,
    SYSC_PER_FUNC_IO063_SEL_MASK = (int)0x7f000000,
    SYSC_PER_FUNC_IO063_SEL_POS = 24,
};

enum SYSC_PER_REG_FUNC_SEL16_FIELD
{
    SYSC_PER_FUNC_IO064_SEL_MASK = (int)0x7f,
    SYSC_PER_FUNC_IO064_SEL_POS = 0,
    SYSC_PER_FUNC_IO065_SEL_MASK = (int)0x7f00,
    SYSC_PER_FUNC_IO065_SEL_POS = 8,
    SYSC_PER_FUNC_IO066_SEL_MASK = (int)0x7f0000,
    SYSC_PER_FUNC_IO066_SEL_POS = 16,
    SYSC_PER_FUNC_IO067_SEL_MASK = (int)0x7f000000,
    SYSC_PER_FUNC_IO067_SEL_POS = 24,
};

enum SYSC_PER_REG_FUNC_SEL17_FIELD
{
    SYSC_PER_FUNC_IO068_SEL_MASK = (int)0x7f,
    SYSC_PER_FUNC_IO068_SEL_POS = 0,
    SYSC_PER_FUNC_IO069_SEL_MASK = (int)0x7f00,
    SYSC_PER_FUNC_IO069_SEL_POS = 8,
    SYSC_PER_FUNC_IO070_SEL_MASK = (int)0x7f0000,
    SYSC_PER_FUNC_IO070_SEL_POS = 16,
    SYSC_PER_FUNC_IO071_SEL_MASK = (int)0x7f000000,
    SYSC_PER_FUNC_IO071_SEL_POS = 24,
};

enum SYSC_PER_REG_FUNC_SEL18_FIELD
{
    SYSC_PER_FUNC_IO072_SEL_MASK = (int)0x7f,
    SYSC_PER_FUNC_IO072_SEL_POS = 0,
    SYSC_PER_FUNC_IO073_SEL_MASK = (int)0x7f00,
    SYSC_PER_FUNC_IO073_SEL_POS = 8,
    SYSC_PER_FUNC_IO074_SEL_MASK = (int)0x7f0000,
    SYSC_PER_FUNC_IO074_SEL_POS = 16,
    SYSC_PER_FUNC_IO075_SEL_MASK = (int)0x7f000000,
    SYSC_PER_FUNC_IO075_SEL_POS = 24,
};

enum SYSC_PER_REG_FUNC_SEL19_FIELD
{
    SYSC_PER_FUNC_IO076_SEL_MASK = (int)0x7f,
    SYSC_PER_FUNC_IO076_SEL_POS = 0,
    SYSC_PER_FUNC_IO077_SEL_MASK = (int)0x7f00,
    SYSC_PER_FUNC_IO077_SEL_POS = 8,
    SYSC_PER_FUNC_IO078_SEL_MASK = (int)0x7f0000,
    SYSC_PER_FUNC_IO078_SEL_POS = 16,
    SYSC_PER_FUNC_IO079_SEL_MASK = (int)0x7f000000,
    SYSC_PER_FUNC_IO079_SEL_POS = 24,
};

enum SYSC_PER_REG_FUNC_SEL20_FIELD
{
    SYSC_PER_FUNC_IO080_SEL_MASK = (int)0x7f,
    SYSC_PER_FUNC_IO080_SEL_POS = 0,
    SYSC_PER_FUNC_IO081_SEL_MASK = (int)0x7f00,
    SYSC_PER_FUNC_IO081_SEL_POS = 8,
    SYSC_PER_FUNC_IO082_SEL_MASK = (int)0x7f0000,
    SYSC_PER_FUNC_IO082_SEL_POS = 16,
    SYSC_PER_FUNC_IO083_SEL_MASK = (int)0x7f000000,
    SYSC_PER_FUNC_IO083_SEL_POS = 24,
};

enum SYSC_PER_REG_FUNC_SEL21_FIELD
{
    SYSC_PER_FUNC_IO084_SEL_MASK = (int)0x7f,
    SYSC_PER_FUNC_IO084_SEL_POS = 0,
    SYSC_PER_FUNC_IO085_SEL_MASK = (int)0x7f00,
    SYSC_PER_FUNC_IO085_SEL_POS = 8,
    SYSC_PER_FUNC_IO086_SEL_MASK = (int)0x7f0000,
    SYSC_PER_FUNC_IO086_SEL_POS = 16,
    SYSC_PER_FUNC_IO087_SEL_MASK = (int)0x7f000000,
    SYSC_PER_FUNC_IO087_SEL_POS = 24,
};

enum SYSC_PER_REG_FUNC_SEL22_FIELD
{
    SYSC_PER_FUNC_IO088_SEL_MASK = (int)0x7f,
    SYSC_PER_FUNC_IO088_SEL_POS = 0,
    SYSC_PER_FUNC_IO089_SEL_MASK = (int)0x7f00,
    SYSC_PER_FUNC_IO089_SEL_POS = 8,
    SYSC_PER_FUNC_IO090_SEL_MASK = (int)0x7f0000,
    SYSC_PER_FUNC_IO090_SEL_POS = 16,
    SYSC_PER_FUNC_IO091_SEL_MASK = (int)0x7f000000,
    SYSC_PER_FUNC_IO091_SEL_POS = 24,
};

enum SYSC_PER_REG_FUNC_SEL23_FIELD
{
    SYSC_PER_FUNC_IO092_SEL_MASK = (int)0x7f,
    SYSC_PER_FUNC_IO092_SEL_POS = 0,
    SYSC_PER_FUNC_IO093_SEL_MASK = (int)0x7f00,
    SYSC_PER_FUNC_IO093_SEL_POS = 8,
    SYSC_PER_FUNC_IO094_SEL_MASK = (int)0x7f0000,
    SYSC_PER_FUNC_IO094_SEL_POS = 16,
    SYSC_PER_FUNC_IO095_SEL_MASK = (int)0x7f000000,
    SYSC_PER_FUNC_IO095_SEL_POS = 24,
};

enum SYSC_PER_REG_FUNC_SEL24_FIELD
{
    SYSC_PER_FUNC_IO096_SEL_MASK = (int)0x7f,
    SYSC_PER_FUNC_IO096_SEL_POS = 0,
    SYSC_PER_FUNC_IO097_SEL_MASK = (int)0x7f00,
    SYSC_PER_FUNC_IO097_SEL_POS = 8,
    SYSC_PER_FUNC_IO098_SEL_MASK = (int)0x7f0000,
    SYSC_PER_FUNC_IO098_SEL_POS = 16,
    SYSC_PER_FUNC_IO099_SEL_MASK = (int)0x7f000000,
    SYSC_PER_FUNC_IO099_SEL_POS = 24,
};

enum SYSC_PER_REG_FUNC_SEL25_FIELD
{
    SYSC_PER_FUNC_IO100_SEL_MASK = (int)0x7f,
    SYSC_PER_FUNC_IO100_SEL_POS = 0,
    SYSC_PER_FUNC_IO101_SEL_MASK = (int)0x7f00,
    SYSC_PER_FUNC_IO101_SEL_POS = 8,
    SYSC_PER_FUNC_IO102_SEL_MASK = (int)0x7f0000,
    SYSC_PER_FUNC_IO102_SEL_POS = 16,
    SYSC_PER_FUNC_IO103_SEL_MASK = (int)0x7f000000,
    SYSC_PER_FUNC_IO103_SEL_POS = 24,
};

enum SYSC_PER_REG_FUNC_SEL26_FIELD
{
    SYSC_PER_FUNC_IO104_SEL_MASK = (int)0x7f,
    SYSC_PER_FUNC_IO104_SEL_POS = 0,
    SYSC_PER_FUNC_IO105_SEL_MASK = (int)0x7f00,
    SYSC_PER_FUNC_IO105_SEL_POS = 8,
    SYSC_PER_FUNC_IO106_SEL_MASK = (int)0x7f0000,
    SYSC_PER_FUNC_IO106_SEL_POS = 16,
    SYSC_PER_FUNC_IO107_SEL_MASK = (int)0x7f000000,
    SYSC_PER_FUNC_IO107_SEL_POS = 24,
};

enum SYSC_PER_REG_FUNC_SEL27_FIELD
{
    SYSC_PER_FUNC_IO108_SEL_MASK = (int)0x7f,
    SYSC_PER_FUNC_IO108_SEL_POS = 0,
    SYSC_PER_FUNC_IO109_SEL_MASK = (int)0x7f00,
    SYSC_PER_FUNC_IO109_SEL_POS = 8,
    SYSC_PER_FUNC_IO110_SEL_MASK = (int)0x7f0000,
    SYSC_PER_FUNC_IO110_SEL_POS = 16,
    SYSC_PER_FUNC_IO111_SEL_MASK = (int)0x7f000000,
    SYSC_PER_FUNC_IO111_SEL_POS = 24,
};

enum SYSC_PER_REG_FUNC_SEL28_FIELD
{
    SYSC_PER_FUNC_IO112_SEL_MASK = (int)0x7f,
    SYSC_PER_FUNC_IO112_SEL_POS = 0,
    SYSC_PER_FUNC_IO113_SEL_MASK = (int)0x7f00,
    SYSC_PER_FUNC_IO113_SEL_POS = 8,
    SYSC_PER_FUNC_IO114_SEL_MASK = (int)0x7f0000,
    SYSC_PER_FUNC_IO114_SEL_POS = 16,
    SYSC_PER_FUNC_IO115_SEL_MASK = (int)0x7f000000,
    SYSC_PER_FUNC_IO115_SEL_POS = 24,
};

enum SYSC_PER_REG_FUNC_SEL29_FIELD
{
    SYSC_PER_FUNC_IO116_SEL_MASK = (int)0x7f,
    SYSC_PER_FUNC_IO116_SEL_POS = 0,
    SYSC_PER_FUNC_IO117_SEL_MASK = (int)0x7f00,
    SYSC_PER_FUNC_IO117_SEL_POS = 8,
    SYSC_PER_FUNC_IO118_SEL_MASK = (int)0x7f0000,
    SYSC_PER_FUNC_IO118_SEL_POS = 16,
    SYSC_PER_FUNC_IO119_SEL_MASK = (int)0x7f000000,
    SYSC_PER_FUNC_IO119_SEL_POS = 24,
};

enum SYSC_PER_REG_FUNC_SEL30_FIELD
{
    SYSC_PER_FUNC_IO120_SEL_MASK = (int)0x7f,
    SYSC_PER_FUNC_IO120_SEL_POS = 0,
    SYSC_PER_FUNC_IO121_SEL_MASK = (int)0x7f00,
    SYSC_PER_FUNC_IO121_SEL_POS = 8,
    SYSC_PER_FUNC_IO122_SEL_MASK = (int)0x7f0000,
    SYSC_PER_FUNC_IO122_SEL_POS = 16,
    SYSC_PER_FUNC_IO123_SEL_MASK = (int)0x7f000000,
    SYSC_PER_FUNC_IO123_SEL_POS = 24,
};

enum SYSC_PER_REG_FUNC_SEL31_FIELD
{
    SYSC_PER_FUNC_IO124_SEL_MASK = (int)0x7f,
    SYSC_PER_FUNC_IO124_SEL_POS = 0,
    SYSC_PER_FUNC_IO125_SEL_MASK = (int)0x7f00,
    SYSC_PER_FUNC_IO125_SEL_POS = 8,
    SYSC_PER_FUNC_IO126_SEL_MASK = (int)0x7f0000,
    SYSC_PER_FUNC_IO126_SEL_POS = 16,
    SYSC_PER_FUNC_IO127_SEL_MASK = (int)0x7f000000,
    SYSC_PER_FUNC_IO127_SEL_POS = 24,
};

enum SYSC_PER_REG_COMP_PIS_FIELD
{
    SYSC_PER_COMP_SEL_MASK = (int)0x7,
    SYSC_PER_COMP_SEL_POS = 0,
};

enum SYSC_PER_REG_PIS_SFT_FIELD
{
    SYSC_PER_PIS_SFT_MASK = (int)0xf,
    SYSC_PER_PIS_SFT_POS = 0,
};

enum SYSC_PER_REG_TIMER_UART_FIELD
{
    SYSC_PER_ADTIM0_OSEL_MASK = (int)0x3,
    SYSC_PER_ADTIM0_OSEL_POS = 0,
    SYSC_PER_ADTIM1_OSEL_MASK = (int)0xc,
    SYSC_PER_ADTIM1_OSEL_POS = 2,
};

#ifdef __cplusplus
}
#endif

#endif